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HM62W16255HCI Series
Wide Temperature Range Version 4M High Speed SRAM (256-kword x 16-bit)
ADE-203-1263A (Z) Rev. 1.0 Nov. 1, 2001 Description
The HM62W16255HCI is a 4-Mbit high speed static RAM organized 256-kword x 16-bit. It has realized high speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. The HM62W16255HCI is packaged in 400-mil 44-pin SOJ and 400-mil 44-pin plastic TSOPII for high density surface mounting.
Features
* * * * * * * * * * Single 3.3 V supply: 3.3 V 0.3 V Access time: 12 ns (max) Completely static memory No clock or timing strobe required Equal access and cycle times Directly TTL compatible All inputs and outputs Operating current: 130 mA (max) TTL standby current: 40 mA (max) CMOS standby current: 5 mA (max) Center VCC and VSS type pinout Temperature range: -40 to +85C
HM62W16255HCI Series
Ordering Information
Type No. Access time Device marking HM62W16255CJPI12 HM62W16255CTTI12 Package 400-mil 44-pin plastic SOJ (CP-44D) 400-mil 44-pin plastic TSOPII (TTP-44DE) HM62W16255HCJPI-12 12 ns HM62W16255HCTTI-12 12 ns
Rev.1, Nov. 2001, page 2 of 17
HM62W16255HCI Series
Pin Arrangement
Pin Description
Pin name A0 to A17 I/O1 to I/O16 Function Address input Data input/output Chip select Output enable Write enable Upper byte select Lower byte select Power supply Ground No connection
CS OE WE UB LB
VCC VSS NC
Rev.1, Nov. 2001, page 3 of 17
HM62W16255HCI Series
Block Diagram
Rev.1, Nov. 2001, page 4 of 17
HM62W16255HCI Series
Operation Table
CS
H L L L L L L L L L Note:
OE WE LB x
H L L L L
UB x x
L H L H L H L H
Mode Standby Output disable Read
VCC current ISB, ISB1 ICC ICC
I/O1-I/O8 High-Z High-Z Output Output High-Z High-Z Input Input High-Z High-Z
I/O9-I/O16 High-Z High-Z Output High-Z Output High-Z Input High-Z Input High-Z
Ref. cycle -- -- Read cycle Read cycle Read cycle -- Write cycle Write cycle Write cycle --
x
H H H H H L L L L
x x
L L H H L L H H
Lower byte read ICC Upper byte read ICC -- Write ICC ICC
x x x x
Lower byte write ICC Upper byte write ICC -- ICC
H: VIH, L: VIL, x: VIH or VIL
Absolute Maximum Ratings
Parameter Supply voltage relative to VSS Voltage on any pin relative to VSS Power dissipation Operating temperature Storage temperature Storage temperature under bias Symbol VCC VT PT Topr Tstg Tbias Value -0.5 to +4.6 -0.5* to VCC + 0.5* 1.0 -40 to +85 -55 to +125 -40 to +85
1 2
Unit V V W C C C
Notes: 1. VT (min) = -2.0 V for pulse width (under shoot) 6 ns 2. VT (max) = VCC + 2.0 V for pulse width (over shoot) 6 ns
Rev.1, Nov. 2001, page 5 of 17
HM62W16255HCI Series
Recommended DC Operating Conditions
(Ta = -40 to +85C)
Parameter Supply voltage Symbol VCC* VSS* Input voltage VIH VIL
3 4
Min 3.0 0 2.0 -0.5*
1
Typ 3.3 0 -- --
Max 3.6 0 VCC + 0.5* 0.8
2
Unit V V V V
Notes: 1. VIL (min) = -2.0 V for pulse width (under shoot) 6 ns 2. VIH (max) = VCC + 2.0 V for pulse width (over shoot) 6 ns 3. The supply voltage with all VCC pins must be on the same level. 4. The supply voltage with all VSS pins must be on the same level.
DC Characteristics
(Ta = -40 to +85C, VCC = 3.3 V 0.3 V, VSS = 0 V)
Parameter Input leakage current Output leakage current Operating power supply current Symbol Min |ILI| |ILO| ICC -- -- -- Typ* -- -- --
1
Max 2 2 130
Unit Test conditions A A mA Vin = VSS to VCC Vin = VSS to VCC Min cycle CS = VIL, Iout = 0 mA Other inputs = VIH/VIL Min cycle, CS = VIH, Other inputs = VIH/VIL f = 0 MHz VCC CS VCC - 0.2 V, (1) 0 V Vin 0.2 V or (2) VCC Vin VCC - 0.2 V IOL = 8 mA IOH = -4 mA
Standby power supply current
ISB ISB1
-- --
-- 2.5
40 5
mA mA
Output voltage
VOL VOH
-- 2.4
-- --
0.4 --
V V
Notes: 1. Typical values are at VCC = 3.3 V, Ta = +25C and not guaranteed.
Rev.1, Nov. 2001, page 6 of 17
HM62W16255HCI Series
Capacitance
(Ta = +25C, f = 1.0 MHz)
Parameter Input capacitance* Note:
1 1
Symbol Cin CI/O
Min -- --
Typ -- --
Max 6 8
Unit pF pF
Test conditions Vin = 0 V VI/O = 0 V
Input/output capacitance*
1. This parameter is sampled and not 100% tested.
Rev.1, Nov. 2001, page 7 of 17
HM62W16255HCI Series
AC Characteristics
(Ta = -40 to +85C, VCC = 3.3 V 0.3 V, unless otherwise noted.) Test Conditions * * * * Input pulse levels: 3.0 V/0.0 V Input rise and fall time: 3 ns Input and output timing reference levels: 1.5 V Output load: See figures (Including scope and jig)
Read Cycle
HM62W16255HCI -12 Parameter Read cycle time Address access time Chip select access time Output enable to output valid Byte select to output valid Output hold from address change Chip select to output in low-Z Output enable to output in low-Z Byte select to output in low-Z Chip deselect to output in high-Z Output disable to output in high-Z Byte deselect to output in high-Z Symbol tRC tAA tACS tOE tLB, tUB tOH tCLZ tOLZ tLBLZ, tUBLZ tCHZ tOHZ tLBHZ, tUBHZ Min 12 -- -- -- -- 3 3 0 0 -- -- -- Max -- 12 12 6 6 -- -- -- -- 6 6 6 Unit ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 Notes
Rev.1, Nov. 2001, page 8 of 17
HM62W16255HCI Series
Write Cycle
HM62W16255HCI -12 Parameter Write cycle time Address valid to end of write Chip select to end of write Write pulse width Byte select to end of write Address setup time Write recovery time Data to write time overlap Data hold from write time Write disable to output in low-Z Output disable to output in high-Z Write enable to output in high-Z Symbol tWC tAW tCW tWP tLBW, tUBW tAS tWR tDW tDH tOW tOHZ tWHZ Min 12 8 8 8 8 0 0 6 0 3 -- -- Max -- -- -- -- -- -- -- -- -- -- 6 6 Unit ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 8 7 9, 10 5 6 Notes
Notes: 1. Transition is measured 200 mV from steady voltage with output load (B). This parameter is sampled and not 100% tested. 2. If the CS or LB or UB low transition occurs simultaneously with the WE low transition or after the WE transition, output remains a high impedance state. 3. WE and/or CS must be high during address transition time. 4. If CS, OE, LB and UB are low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 5. tAS is measured from the latest address transition to the latest of CS, WE, LB or UB going low. 6. tWR is measured from the earliest of CS, WE, LB or UB going high to the first address transition. 7. A write occurs during the overlap of low CS, low WE and low LB or low UB. 8. tCW is measured from the later of CS going low to the end of write. 9. tLBW is measured from the later of LB going low to the end of write. 10. tUBW is measured from the later of UB going low to the end of write.
Rev.1, Nov. 2001, page 9 of 17
HM62W16255HCI Series
Timing Waveforms
Read Timing Waveform (1) (WE = VIH)
Rev.1, Nov. 2001, page 10 of 17
HM62W16255HCI Series
Read Timing Waveform (2) (W E = VIH, L B = VIL, U B , = VIL) W
Rev.1, Nov. 2001, page 11 of 17
HM62W16255HCI Series
Write Timing Waveform (1) (LB, UB Controlled)
Rev.1, Nov. 2001, page 12 of 17
HM62W16255HCI Series
Write Timing Waveform (2) (WE Controlled)
Rev.1, Nov. 2001, page 13 of 17
HM62W16255HCI Series
Write Timing Waveform (3) (CS Controlled)
Rev.1, Nov. 2001, page 14 of 17
HM62W16255HCI Series
Package Dimensions
HM62W16255HCJPI Series (CP-44D)
Rev.1, Nov. 2001, page 15 of 17
HM62W16255HCI Series
HM62W16255HCTTI Series (TTP-44DE)
Rev.1, Nov. 2001, page 16 of 17
HM62W16255HCI Series
Disclaimer
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
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Rev.1, Nov. 2001, page 17 of 17

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